FIG. 8 is an outlined circuit diagram showing an example configuration of a conventional series regulator. In the series regulator shown in FIG. 8, voltage of voltage source Vin is applied to drain N1 of an n-type MOS transistor, and capacitor CL and current load IL are connected between source N2 and the ground line.
In addition, resistors 2a and 2b for voltage detection are connected in series between source N2 of n-type MOS transistor 1 and the ground line, and midpoint N4 between them is connected to the negative (−) input terminal of differential amplifier circuit 3. The voltage of voltage source VR is applied to the positive (+) input terminal of differential amplifier circuit 3. The voltage difference between said positive (+) input terminal and negative (−) input terminal is amplified by differential amplifier circuit 3 and input to the gate of n-type MOS transistor 1.
In the series regulator with the aforementioned configuration, the error between the detected value of the source voltage of n-type MOS transistor 1 and its target value is amplified by differential amplifier circuit 3 and fed back to gate N4 of n-type MOS transistor 1 in order to regulate the output voltage supplied to current load IL.
For example, when the source voltage of n-type MOS transistor 1 increases, the voltage of node N3 where said voltage is divided by resistors 2a and 2b also increases. Accordingly, the output voltage of differential amplifier circuit 3 drops, and the source voltage of n-type MOS transistor 1 drops. Similarly, when the voltage of source N2 of n-type MOS transistor 1 drops, voltage of node N3 drops, the output voltage of differential amplifier circuit 3 increases, and the source voltage of n-type MOS transistor increases.
As described above, negative feedback is applied to the source voltage of n-type MOS transistor 1 in order for the voltage of node N3 and the voltage of voltage source VR to become almost the same.
Incidentally, in the case of the series regulator shown in FIG. 8, when the load current due to current load IL changes from a low current to a very small current suddenly, the output voltage control cannot be carried out in time to handle said change in the load current, and the current in current load IL ends up flowing into capacitor CL1, so that the output voltage increases. Once capacitor CL1 gets charged, it takes a long time for the charge in capacitor CL1 to be discharged because the very small current from current load IL and the current in resistors 2a and 2b are the only currents which can be used to discharge said charge, so that a condition in which the output voltage is higher than the target voltage continues for a long time.
As described above, if the condition in which the output voltage is higher than the target voltage continues, a part having a small voltage tolerance suffers a voltage stress, resulting in major problems, such as malfunctioning, a deteriorated characteristic, and an increased defect rate. In addition, although it is possible to lower the resistance values of resistors 2a and 2b to increase the current discharged from capacitor CL in order to increase the discharging speed, the amount of current consumed by resistors 2a and 2b increases under normal conditions where the output voltage and the target voltage match when this method is adopted, resulting in a problem of a small increase in the power consumption.
The present invention was made in consideration of said situation, and its purpose is to present a regulator circuit capable of reducing the increase in the output voltage when the load current drops suddenly without increasing the power consumption under normal conditions.